HPC - Software Tools & Optimizations#
A Deep Dive into LDS Optimizations on AMD Instinct MI450 GPUs
Learn how to optimize LDS traffic in Gluon kernels on AMD Instinct MI450 GPUs using transposed loads and partition-conflict-free layouts.
Memory Instruction Scheduling for Lock-Stepped Kernels on AMD Instinct™ MI300X: Introducing the Series
Explore how instruction scheduling eases stalls on AMD Instinct MI300X in a new blog series. This intro covers the motivating example and methodology.
Using ODC to Accelerate AMD SFT Training
Learn how we ported ODC on-demand P2P communication to AMD Instinct MI300X to cut FSDP bubbles and speed up variable-length SFT training.
AMD GPU Operator v1.5.0: DRA Support, Automated GPU Node Recovery, and Expanded Kubernetes Infrastructure Control
Discover how AMD GPU Operator v1.5.0 improves GPU scheduling, automates node recovery, and expands Kubernetes control.
Attention Decode on AMD MI450 GPUs: A Gluon Kernel Optimization Guide
Learn how to design a high-performance attention decode kernel on AMD MI450 GPUs using Gluon.
Spur: Modern GPU Job Scheduling for HPC and AI Workloads
Explore how Spur addresses pain points in GPU cluster management and how Spur-Cloud extends the platform into a complete GPU-as-a-Service solution.
Introducing ROCm™ AMD Infinity Context: A Purpose-Built KV Cache Tier for Distributed Inference
Explore ROCm AMD Infinity Context (AIC), AMD's open KV cache tier built on AMD Infinity Storage for distributed LLM inference.
Understanding Attention Algorithms and Their Backends for Image and Video Generation
Practical guide to attention backends in ComfyUI on AMD describing how to optimize performance, memory, and stability with the right configuration.
SPIR-V on ROCm: A Portable IR for AMD GPUs
Learn how SPIR-V brings compile-once, specialize-on-device portability to AMD GPUs — with a reproducible HIP benchmark, trade-off analysis, and quick-start guide.
Performance Profiling on AMD GPUs – Part 5: Profiling-Driven Kernel Optimization with an AI Code-Assist Tool
Ready to slash HIP kernel runtimes? See how ROCm profiling + an AI code-assist agent delivered a 28.3× speedup on AMD Instinct MI250.
Porting High-Performance HIP Kernels to FlyDSL
This blog post shows how to port HIP C++ GPU kernels to FlyDSL, AMD's new Python DSL, matching hand-tuned C++ performance with less code.
OpenXLA and JAX - ROCm Support and the State of CI
Learn how OpenXLA and JAX run on AMD ROCm: what landed this year, how every PR is gated on real Instinct hardware, and how to get started.