Posts by Amanzhol Salykov
Porting High-Performance HIP Kernels to FlyDSL
- 09 July 2026
In our series of posts we have explored how to utilize Matrix Core instructions and how to design high-performance GEMM kernels using HIP C++. In this post we’ll show how to port those kernels to FlyDSL, a new Python DSL developed at AMD to simplify kernel development and testing. By working through real-world examples, we’ll explore the key concepts of FlyDSL and how they map to low-level HIP C++ code. Finally, we’ll show how — despite being higher-level — FlyDSL kernels can match or even exceed the performance of hand-tuned C++ kernels with a fraction of the complexity.
Deep Dive Into 4-Wave Interleave FP8 GEMM
- 27 May 2026
Our previous two posts in this GEMM optimization series covered Matrix Core instructions and 8-wave ping-pong FP8 GEMM design. Here we discuss another algorithm design introduced by HipKittens - 4-wave interleave, which further improves the performance of the 8-wave ping-pong implementation. For the most complete understanding, we recommend reading this post alongside the source code.
FP8 GEMM Optimization on AMD CDNA™4 Architecture
- 10 March 2026
This blog post continues our previous blog Matrix Core Programming on AMD CDNA™3 and CDNA™4 Architecture, which introduced Matrix Cores and demonstrated how to use them in HIP kernels.
Matrix Core Programming on AMD CDNA™3 and CDNA™4 architecture
- 30 September 2025
In this blog post, we walk through how to use Matrix Cores in HIP kernels, with a focus on low-precision data types such as FP16, FP8, and FP4, as well as the new family of Matrix Core instructions with exponent block scaling introduced in the AMD CDNA™4 architecture. Through code examples and illustrations, we provide the necessary knowledge to start programming Matrix Cores, covering modern low-precision floating-point types, the Matrix Core compiler intrinsics, and the data layouts required by the Matrix Core instructions.