AI Blogs#
An Educational GEMM Ladder for Helios GPUs
Build high-performance BF16 GEMM kernels on Helios GPUs with HipKittens, from a naive baseline to optimized schedules.
Iteratively Tuning hipBLASLt TensileLite Kernels: A Smaller Search, a Faster Kernel
Learn why a small iterative search beats a big one-shot sweep for hipBLASLt TensileLite kernels, in less time and with no risk of regression.
veRL on AMD: Production-Ready RL Post-Training on ROCm
Run veRL RL post-training on AMD Instinct GPUs with a turnkey ROCm container, AITER-accelerated rollout, and validated accuracy on MI300 and MI355.
Efficiently Serving NVFP4 Models on AMD Instinct™ MI350X/MI355X Accelerators via Online NVFP4 to Quark MXFP4 Requantization
Serve NVFP4 models on MI350X/MI355X via SGLang's online NVFP4 to MXFP4 requantization: no preprocessing, minimal accuracy impact, native throughput.
Enabling DeepSeek-V4-Flash Training on AMD Instinct MI355X GPUs with Primus
DeepSeek-V4-Flash training on AMD Instinct GPUs with Primus: model architecture introduction, performance projection, kernel optimizations, and how to reproduce.
Optimizing ATOM and vLLM-ATOM for High-Interactivity Inference
Cut per-token latency on AMD Instinct MI355X GPUs: see how ATOM, vLLM-ATOM, and AITER strip fixed costs out of the LLM decode path.
4-bit KV Caching in LMCache: Offloading Quantized KV Beyond HBM for Context-Heavy Agents on AMD MI355X
Combining 4-bit KV quantization (TurboQuant) with KV offload (LMCache) on AMD MI355X nearly doubles serving goodput for long-context agents.
Serving 64Mi-Token Contexts on One AMD Instinct™ MI355X Node
Explore how one 8-GPU AMD MI355X node serves Kimi Linear from 1K to 64M tokens under vLLM—and the TTFT and decode throughput behind the run.
DI Series: Scaling GLM-5.1-FP8 to 64 MI300X GPUs
Scale GLM-5.1-FP8 long-context serving beyond a single node on AMD Instinct MI300X with WideEP prefill-decode disaggregation and MoRI.
Exploring XGBoost: A Deep Dive
A single source explanation of XGBoost features and its working principles.
Scaling RL with verl on AMD Instinct MI355X: Async Walkthrough and Sync Benchmark
Scale RLHF on AMD Instinct MI355X with verl's fully async trainer. Hands-on GRPO + DAPO examples.
Memory Instruction Scheduling for Lock-Stepped Kernels on AMD Instinct™ MI300X: Introducing the Series
Explore how instruction scheduling eases stalls on AMD Instinct MI300X in a new blog series. This intro covers the motivating example and methodology.